ON-BOARD PACKET BUFFERING
Napatech accelerators provide on-board memory for buffering of Ethernet frames. Buffering assures guaranteed delivery of data, even when there is congestion. There are three potential sources of congestion: the PCI interface, the server platform, and the analysis application.
PCI interfaces provide a fixed bandwidth for transfer of data from the accelerator to the application. For some accelerators, this can limit the amount of data that can be transferred from the network to the application. For example, an 8-lane PCIe Gen3 interface can transfer up to 50 Gbps of data to the application. If the network speed is 100 Gbps, a burst of data cannot be transferred over the PCIe Gen3 interface in real time, since the data rate is twice the maximum transferable rate that can be transferred over the PCIe Gen3 interface. In this case, the onboard packet buffering on the Napatech accelerator can absorb the burst and ensure that none of the data is lost, allowing the frames to be transferred once the burst has passed.
Servers and applications can be configured in such a way that congestion can occur in the server infrastructure or in the application itself. The CPU cores can be busy processing or retrieving data from remote caches and memory locations, which means that new Ethernet frames cannot be transferred from the accelerator.
In addition, the application can be configured with only one or a few processing threads, which can result in the application being overloaded, meaning that new Ethernet frames cannot be transferred. With onboard packet buffering, the Ethernet frames can be delayed until the server or the application is ready to accept them. This ensures that no Ethernet frames are lost and that all the data is made available for analysis when needed.