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MWC Barcelona 2020

Unlock the Promise of 5G

At MWC Barcelona 2020, we are thrilled to be demonstrating how our FPGA SmartNIC software and hardware can scale your 5G mobile NFV infrastructure and accelerate networking and security applications for a variety of mobile use cases.

With the number of 5G mobile devices scaling to billions in the coming years, your mobile edge computing solution can realize significant performance improvements through FPGA acceleration. This is achieved by offloading the virtual switching and flow-aware passive and inline application processing with zero packet loss up to 100 Gbps.


Visit us in Hall 6 Stand 6I15 as we demonstrate:

  • 100 Gbps accelerated Open vSwitch offload with market leading numbers:
    6x performance gain compared to OVS DPDK and 60x gain compared to OVS kernel
  • Stateful passive monitoring and inline match/action flow processing with outstanding results:
    200 Gbps of throughput, 100 million bidirectional flows, 1 million flow setups per second


With Napatech reconfigurable SmartNICs, numerous NFV acceleration solutions can be achieved reusing the same hardware from edge to core with varied software loads for different application and network architectures.

Join our 5G Tour for guidance on how to improve your 5G mobile NFV infrastructure and architecture. Sign up on the Topic Tours page under 5G Tour.

Contact us at to set up a meeting.


Stand: Hall 6 Stand 6I15

Where: Barcelona, Spain

When: 24–27 February 2020

Learn more about MWC Barcelona 2020

Sign up for our 5G Tour

Unlock the promise of 5G

To unlock the promise of 5G, mobile network operators are making the shift from proprietary hardware to standard server platforms. This will allow them to scale their infrastructure to account for the dramatic throughput 5G offers as well as the incredible increase in the number of endpoints.

To realize this promise of 5G, a new level of performance can be achieved by offloading network and security workloads for virtualized networking functions (VNFs) to dedicated offload processing elements based on programmable FPGA technology.



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