With the acquisition of Altera, Intel® has enabled the Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA. This new card allows FPGA developers to create AFU (Accelerator Functional Units) that can be deployed on the card and bring FPGA-based value-add to the application.
The OPAE framework
Intel has developed a framework SDK – the Open Programmable Acceleration Engine (OPAE) – that operates with terms like blue and green bitstreams, using the colors to describe the internals of the Intel FPGA. The blue bitstreams are FPGA functional blocks delivered by Intel to make the card work. It contains IO logic for all the surrounding peripherals like PCI, SDRAM, and QSFP+. The green bitstream is where the user code (AFU) is located. The blue bitstream abstracts the IO via standardized APIs enabling the green bitstream to be easily ported to new blue bitstreams on other HW platforms.
The OPAE framework strives to ensure that the developer of an AFU only needs to concern him/herself with the AFU specifics and not the bring-up of the entire FPGA. The server application layer of the OPAE contains a driver layer giving the user access to acquire the FPGA, reset the FPGA, read/write to the FPGA, etc., all via standardized functions. The OPAE framework also provides functions like memory allocate, which can be seen both by the FPGA and the CPU.
The Napatech firmware is a green bitstream that interfaces with the blue bitstream components and enables the Napatech driver suite to interact with the Napatech firmware as if it were Napatech hardware. Normally, Napatech applies both blue and green bitstreams on its own hardware, so using only the green bitstream has been challenging, yet successful.
The PAC hardware consists of:
- a QSFP+ enabling a single 40Gbps or 4x10Gbps (via breakout cables)
- a Intel Arria 10 GX FPGA
- 8 GB DDR-4 memory
- x8 PCIe (~50Gbps) host interface
- flash to store the FPGA image
Image by courtesy of Intel
Napatech has a long history of creating its own SmartNICs, but with the collaboration between Intel and Napatech, it is now possible to buy an Intel FPGA based NIC and get Napatech software to run on this non-Napatech hardware. The Napatech software on the Intel hardware enables full 40Gbps zero packet loss RX/TX both on 4x10Gbps and 1x40Gbps. Besides zero packet loss, key Napatech features like deduplication, correlation key generation, flow matching, pattern match, etc. become available as does the highly flexible tuple matcher used for load distribution of traffic. Napatech has enabled the Intel card to work as a plug-n-play solution for several monitoring/security applications like Suricata, Snort, Bro as well as the TRex traffic generator which means that it is also integrated into DPDK when running the Napatech firmware.
With the Intel PAC running Napatech Software, Intel now has a hardware platform that can claim zero packet loss at 40Gbps, which to my knowledge has not previously been possible. We have been testing internally with both the PAC and Intel X710 – and only the PAC with Napatech Software can ensure zero packet loss. Running e.g. Suricata on X710, the packet loss starts to occur at ~ 1Gbps, but with the Intel PAC, it runs without loss at ~40Gbps.
I see great potential for the PAC platform and OPAE going forward and look very much forward to seeing what use cases it will fulfill and how the platform will evolve. Hopefully the PAC will enable more FPGA business, both from a hardware and firmware perspective. I don’t think the current PAC is a one-fits-all platform, but it can be the catalyst to spin-off a general interest in FPGA and other form factor boards that all feature the OPAE to enable portability from an application point of view. And in the end, that is what matters: that the application is accelerated.
Intel’s next PAC with a Stratix 10 looks interesting and much more similar to the Napatech hardware products, so let’s see what the future brings.