200G Performance Solution
Built for performance on an epic scale with two
PCI-SIG certified NT100E3-1-PTP FPGA SmartNICs.
For any link speed at any time
PLUG & PLAY
Out of the box solution
Accelerate your application
Synchronize multiple servers
Multiple FPGA SmartNICs in one server
Full throughput with zero packet loss
Multiple speeds in one server
More powerful server usage
Key Napatech SmartNIC features
200G Performance Features
Full line-rate packet capture
Multi-port packet sequence
Multi-port packet sequence and merge
Intelligent Multi-CPU distribution
- Distribution per port: all frames captured on a physical port are transferred to the same CPU or a range of CPU cores for processing
- Distribution per traffic type: frames of the same protocol type are transferred to the same CPU or a range of CPU cores for processing
- Distribution by flows: frames with the same hash value are sent to the same CPU or a range of CPU cores for processing
- Combinations of the above
Hardware Time Stamp
- 2 Windows formats with 10-ns or 100-ns resolution
- Native UNIX format with 10-ns resolution
- 2 PCAP formats with 1-ns or 1000-ns resolution
Optimum Cache Utilization
On-Board Packet Buffering
Napatech FPGA SmartNICs provide on-board memory for buffering of Ethernet frames. Buffering assures guaranteed delivery of data, even when there is congestion in the delivery of data to the application. There are three potential sources of congestion: the PCI interface, the server platform, and the analysis application.
PCI interfaces provide a fixed bandwidth for transfer of data from the SmartNIC to the application. This limits the amount of data that can be continuously transferred from the network to the application. For example, a 16-lane PCIe Gen3 interface can transfer up to 115 Gbps of data to the application. If the network speed is 2×100 Gbps, a burst of data cannot be transferred over the PCIe Gen3 interface in real time, since the data rate is twice the maximum PCIe bandwidth. In this case, the onboard packet buffering on the Napatech SmartNIC can absorb the burst and ensure that none of the data is lost, allowing the frames to be transferred once the burst has passed.
Servers and applications can be configured in such a way that congestion can occur in the server infrastructure or in the application itself. The CPU cores can be busy processing or retrieving data from remote caches and memory locations, which means that new Ethernet frames cannot be transferred from the SmartNIC.
In addition, the application can be configured with only one or a few processing threads, which can result in the application being overloaded, meaning that new Ethernet frames cannot be transferred. With onboard packet buffering, the Ethernet frames can be delayed until the server or the application is ready to accept them. This ensures that no Ethernet frames are lost and that all the data is made available for analysis when needed.
IP fragment handling
In-line application support
The Napatech SmartNIC family supports 200 Gbps in-line applications enabling customers to create powerful, yet flexible in-line solutions on standard servers. The more CPU-demanding the application is, and the higher the speeds of links, the higher the value of this solution. Features include:
- Full throughput bidirectional Rx/Tx up to 200G link speed for any packet size
- Multi-core processing support with up to 128 Rx/Tx streams per accelerator
- Customizable hash-based load distribution
- Efficient zero copy roundtrip from Rx to Tx
- Single bit flip selection to discard or forward each individual packet
- Typical 50 us roundtrip latency from Rx to Tx fiber
For network security purposes, different traffic scenarios need to be recreated and simulated to toughen the infrastructure. The packets also need to be replayed to understand delays and disruptions caused by traffic bursts/peaks to improve Quality of Service (QoS). With Napatech FPGA SmartNICs, it is easy to setup and specify the test scenario to replay the same PCAP files from real network events at 10G, 40G and 100G link speeds.
Access control and authentication solutions can now implement full line rate solutions, that can cope with small packets, with a SmartNIC that does robust packet delivery at high network loads. Session control propels traffic in and out of the SmartNIC, at low latency (<5us), while simultaneously copying a subset to the host CPU for analysis. With the session control feature, inline use cases can benefit from low latency at speeds 1-100G.
Get highest precision time stamping for traffic that needs to be redistributed to multiple network devices. Napatech FPGA SmartNICs systems can forward and/or split traffic captured on a single tapping point to a cluster of servers for processing, without using additional equipment. This is achieved by the Napatech FPGA SmartNICs acting as both Smart Taps and packet capture devices and is apt for multi-box solutions with single tapping points. This feature eliminates the need to implement expensive SmartTaps, time stamping switches, packet brokers and other time sync components.
CPU socket load balancer
CPU socket load balancer
Further enhance your CPU utilization with the CPU Socket Load Balancer capability offered by Napatech NT40E3 FPGA SmartNICs. Improve CPU performance by up to 30% per server for 4x10G analysis with Napatech FPGA SmartNICs that can efficiently distribute traffic to 2 CPU sockets, making the packets available to multiple analysis threads on both CPU sockets, simultaneously. This frees up CPU resources needed for copying data between the two sockets and eliminates the need for expensive QPI bus transfers.
2xNT100E3-1-PTP FPGA SmartNICs
2xNT100E3-1-PTP-NEBS FPGA SmartNICs
Accelerate your time-to-market and reduce risk
Napatech Software Suite provides an efficient migration path by allowing you to mix and match ports and speeds. An advanced cooling design assures the required airflow while sensors monitor voltage, power, and temperature.
A common API is provided for all Napatech FPGA SmartNICs allowing plug-and-play operation. An intuitive, easy-to-learn, yet powerful programming language is also provided to allow dynamic, on-the-fly configuration of filtering and intelligent multi-CPU distribution on Napatech FPGA SmartNICs.
Used across industries
Telecom network management
Quality of experience optimization
Application performance management
Security data collection
Ultimate tech specs.
|TECH SPECS||NAPATECH 200G PERFORMANCE SOLUTION|
|Hardware Time Stamp|
|On-Board IEEE 1588-2008 (PTP V2)|
|Pluggable Options for Time Synchronization|
|Host Interface and Memory|
|Environment for NT200C01-2|
|Regulatory Approvals and Compliances|