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Link™ NT200A02 SmartNIC


The Link™ NT200A02 SmartNIC enables 8x10G, 2x40G or 2x100G applications, depending on which software you select. This offers the flexibility to create high-performance solutions in 1U server platforms for existing 40G network infrastructure deployed today, with the freedom to repurpose the solution for 100G installations when necessary. This 2-in-1 product not only saves rack space and reduces the overall cost of the solution – it also provides outstanding agility and scalability for the future.



For any link speed at any time


From 1-100G



Out of the box solution


Multiple FPGA SmartNICs in one server


Synchronize multiple servers



Accelerate your application


Full throughput with zero packet loss



Multiple speeds in one server


More powerful server usage

Key Napatech SmartNIC features

Link™ NT200A02 SmartNIC Features

Line-rate performance

Full line-rate packet capture

Napatech FPGA SmartNICs are highly optimized to capture network traffic at full line-rate, with almost no CPU load on the host server, for all frame sizes. Zero-loss packet capture is critical for applications that need to analyze all the network traffic. If anything needs to be discarded, it is a matter of choice by the application, not a limitation of the SmartNIC. 
Standard network interface cards (NICs) are not designed for analysis applications where all traffic on a connection or link needs to be analyzed. NICs are designed for communication where data that is not addressed to the sender or receiver is simply discarded. This means that NICs are not designed to have the capacity to handle the amount of data that is regularly transmitted in bursts on Ethernet connections. In these burst situations, all of the bandwidth of a connection is used, requiring the capacity to analyze all Ethernet frames. Napatech FPGA SmartNICs are designed specifically for this task and provide the maximum theoretical packet capture capacity.

Multi-port packet sequence

Multi-port packet sequence and merge

Napatech FPGA SmartNICs typically provide multiple ports. Ports are usually paired, with one port receiving upstream packets and another port receiving downstream packets. Since these two flows going in different directions need to be analyzed as one, packets from both ports must be merged into a single analysis stream. Napatech FPGA SmartNICs can sequence and merge packets received on multiple ports in hardware using the precise time stamps of each Ethernet frame. This is highly efficient and offloads a significant and costly task from the analysis application.

There is a growing need for analysis appliances that are able to monitor and analyze multiple points in the network, and even provide a network-wide view of what is happening. Not only does this require multiple FPGA SmartNICs to be installed in a single appliance, but it also requires that the analysis data from all ports on every accelerator be correlated.

With the Napatech Software Suite, it is possible to sequence and merge the analysis data from multiple FPGA SmartNICs into a single analysis stream. The merging is based on the nanosecond precision time stamps of each Ethernet frame, allowing a time-ordered merge of individual data streams.


Intelligent Multi-CPU distribution

Modern servers provide unprecedented processing power with multi-core CPU implementations. This makes standard servers an ideal platform for appliance development. But, to fully harness the processing power of modern servers, it is important that the analysis application is multi-threaded and that the right Ethernet frames are provided to the right CPU core for processing. Not only that, but the frames must be provided at the right time to ensure that analysis can be performed in real time.

Napatech Multi-CPU distribution is built and optimized from our extensive knowledge of server architecture, as well as real life experience from our customers.

Napatech FPGA SmartNICs ensure that identified flows of related Ethernet frames are distributed in an optimal way to the available CPU cores. This ensures that the processing load is balanced across the available processing resources, and that the right frames are being processed by the right CPU cores.

With flow distribution to multiple CPU cores, the throughput performance of the analysis application can be increased linearly with the number of cores, up to 128. Not only that, but the performance can also be scaled by faster processing cores. This highly flexible mechanism enables many different ways of designing a solution and provides the ability to optimize for cost and/or performance.

Napatech FPGA SmartNICs support different distribution schemes that are fully configurable:

  • Distribution per port: all frames captured on a physical port are transferred to the same CPU or a range of CPU cores for processing
  • Distribution per traffic type: frames of the same protocol type are transferred to the same CPU or a range of CPU cores for processing
  • Distribution by flows: frames with the same hash value are sent to the same CPU or a range of CPU cores for processing
  • Combinations of the above

Time stamping

Hardware Time Stamp

The ability to establish the precise time when frames have been captured is critical to many applications. 
To achieve this, all Napatech FPGA SmartNICs are capable of providing a high-precision time stamp, sampled with 1 nanosecond resolution, for every frame captured and transmitted.
At 10 Gbps, an Ethernet frame can be received and transmitted every 67 nanoseconds. At 100 Gbps, this time is reduced to 6.7 nanoseconds. This makes nanosecond-precision time-stamping essential for uniquely identifying when a frame is received. This incredible precision also enables you to sequence and merge frames from multiple ports on multiple FPGA SmartNICs into a single, time-ordered analysis stream.
In order to work smoothly in the different operating systems supported, Napatech FPGA SmartNICs support a range of industry standard time stamp formats, and also offer a choice of resolution to suit different types of applications.
64-bit time stamp formats:
  • Native UNIX format with 1-ns or or 10-ns resolution
  • 2 PCAP formats with 1-ns or 1000-ns resolution

Cache optimization

Optimum Cache Utilization 

Napatech FPGA SmartNICs use a buffering strategy that allocates a number of large memory buffers where as many packets as possible are placed back-to-back in each buffer.  Using this implementation, only the first access to a packet in the buffer is affected by the access time to external memory. Thanks to cache pre-fetch, the subsequent packets are already in the level 1 cache before the CPU needs them. As hundreds or even thousands of packets can be placed in a buffer, a very high CPU cache performance can be achieved leading to application acceleration.
Buffer configuration can have a dramatic effect on the performance of analysis applications. Different applications have different requirements when it comes to latency or processing. It is therefore extremely important that the number and size of buffers can be optimized for the given application. Napatech FPGA SmartNICs make this possible. 
The flexible server buffer structure supported by Napatech FPGA SmartNICs can be optimized for different application requirements. For example, applications needing short latency can have frames delivered in small chunks, optionally with a fixed maximum latency. Applications without latency requirements can benefit data delivered in large chunks, providing more effective server CPU processing by having the data. Applications that need to correlate information distributed across packets can configure larger server buffers (up to 128 GB).
Up to 128 buffers can be configured and combined with Napatech multi-CPU distribution (see “Multi-CPU distribution”).

Packet buffering

On-Board Packet Buffering

Napatech FPGA SmartNICs provide on-board memory for buffering of Ethernet frames. Buffering assures guaranteed delivery of data, even when there is congestion in the delivery of data to the application. There are three potential sources of congestion: the PCI interface, the server platform, and the analysis application.

PCI interfaces provide a fixed bandwidth for transfer of data from the SmartNIC to the application. This limits the amount of data that can be continuously transferred from the network to the application. For example, a 16-lane PCIe Gen3 interface can transfer up to 115 Gbps of data to the application. If the network speed is 2×100 Gbps, a burst of data cannot be transferred over the PCIe Gen3 interface in real time, since the data rate is twice the maximum PCIe bandwidth. In this case, the onboard packet buffering on the Napatech SmartNIC can absorb the burst and ensure that none of the data is lost, allowing the frames to be transferred once the burst has passed.

Servers and applications can be configured in such a way that congestion can occur in the server infrastructure or in the application itself. The CPU cores can be busy processing or retrieving data from remote caches and memory locations, which means that new Ethernet frames cannot be transferred from the SmartNIC.

In addition, the application can be configured with only one or a few processing threads, which can result in the application being overloaded, meaning that new Ethernet frames cannot be transferred. With onboard packet buffering, the Ethernet frames can be delayed until the server or the application is ready to accept them. This ensures that no Ethernet frames are lost and that all the data is made available for analysis when needed.


Tunneling Support

In mobile networks, all subscriber Internet traffic is carried in GTP (GPRS Tunneling Protocol) or IP-in-IP tunnels between nodes in the mobile core.  IP-in-IP tunnels are also used in enterprise networks. Monitoring traffic over interfaces between these nodes is crucial for assuring Quality of Service (QoS).
Napatech FPGA SmartNICs decode these tunnels, providing the ability to correlate and load balance based on flows inside the tunnels. Analysis applications can use this capability to test, secure, and optimize mobile networks and services. To effectively analyze the multiple services associated with each subscriber, it is important to separate them and analyze each one individually. Napatech FPGA SmartNICs have the capability to identify the contents of tunnels, allowing for analysis of each service used by a subscriber. This quickly provides the needed information to the application, and allows for efficient analysis of network and application traffic. The Napatech features for frame classification, flow identification, filtering, coloring, slicing, and intelligent multi-CPU distribution can thus be applied to the contents of the tunnel rather than the tunnel itself, leading to a more balanced processing and a more efficient analysis.
GTP and IP-in-IP tunneling are powerful features for telecom equipment vendors who need to build mobile network monitoring products. With this feature, Napatech can off-load and accelerate data analysis, allowing customers to focus on optimizing the application, and thereby maximizing the processing resources in standard servers.

IP fragments

IP fragment handling

IP fragmentation occurs when larger Ethernet frames need to be broken into several fragments in order to be transmitted across the network. This can be due to limitations in certain parts of the network, typically when GTP tunneling protocols are used. Fragmented frames are a challenge for analysis applications, as all fragments must be identified and potentially reassembled before analysis can be performed. Napatech FPGA SmartNICs can identify fragments of the same frame and ensure that these are associated and sent to the same CPU core for processing. This significantly reduces the processing burden for analysis applications.

In-line mode

In-line application support

The Napatech SmartNIC family supports 40 Gbps in-line applications enabling customers to create powerful, yet flexible in-line solutions on standard servers. The more CPU-demanding the application is, and the higher the speeds of links, the higher the value of this solution. Features include:

  • Full throughput bidirectional Rx/Tx up to 40G link speed for any packet size
  • Multi-core processing support with up to 128 Rx/Tx streams per accelerator
  • Customizable hash-based load distribution
  • Efficient zero copy roundtrip from Rx to Tx
  • Single bit flip selection to discard or forward each individual packet
  • Typical 50 us roundtrip latency from Rx to Tx fiber

Traffic replay

Traffic replay

For network security purposes, different traffic scenarios need to be recreated and simulated to toughen the infrastructure. The packets also need to be replayed to understand delays and disruptions caused by traffic bursts/peaks to improve Quality of Service (QoS). With Napatech FPGA SmartNICs, it is easy to setup and specify the test scenario to replay the same PCAP files from real network events at 40G and 100G link speeds.

Session control

Session control

Access control and authentication solutions can now implement full line rate solutions, that can cope with small packets, with a SmartNIC that does robust packet delivery at high network loads. Session control propels traffic in and out of the SmartNIC, at low latency (<5us), while simultaneously copying a subset to the host CPU for analysis. With the session control feature, inline use cases can benefit from low latency at speeds 1-100G.

Traffic forwarding

Traffic forwarding

Get highest precision timestamping for traffic that needs to be redistributed to multiple network devices. Napatech FPGA SmartNICs systems can forward and/or split traffic captured on a single tapping point to a cluster of servers for processing, without using additional equipment. This is achieved by the Napatech FPGA SmartNICs acting as both Smart Taps and packet capture devices and is apt for multi-box solutions with single tapping points. This feature eliminates the need to implement expensive SmartTaps, time stamping switches, packet brokers and other time sync components.

Link™ NT200A02-SCC SmartNIC

Link™ NT200A02-NEBS SmartNIC

Accelerate your time-to-market and reduce risk

Napatech Software Suite provides an efficient migration path by allowing you to mix and match ports and speeds. An advanced cooling design assures the required airflow while sensors monitor voltage, power, and temperature.

A common API is provided for all Napatech FPGA SmartNICs allowing plug-and-play operation. An intuitive, easy-to-learn, yet powerful programming language is also provided to allow dynamic, on-the-fly configuration of filtering and intelligent multi-CPU distribution on Napatech FPGA SmartNICs.

Used across industries

Cyber security

Detect Advanced Persistent Threats (APT) and other breaches to your network at 8x10G, 2x40G or 2x100G – no activity goes unnoticed.

Across industries, cyber assaults are accumulating at alarming rates. Hackers are constantly refining their tactics and repeatedly circumventing static defenses.

To identify any suspicious activity on your network, you need full visibility at all times. Even a marginal fraction of information lost can potentially compromise the safety of your business. Who has been on your network, what have they done, and when exactly did they do it? A myriad of intelligent security solutions are available to help you answer these questions – but to deliver the needed insights, they need fully reliable data. And with network speeds advancing to 40G or 100G, the challenge of attaining reliable data is firmly growing.

With the Napatech Link™ NT200A02 SmartNIC, we help you ensure that no data is lost and no activity goes unnoticed. Napatech provides guaranteed delivery of network data, and supply all the information needed for effective forensic analysis in real-time, even at speeds up to 40G or 100G. This means a much shorter response time, improved mitigation and ultimately a reinforced security. 

Telecom operators

Break the cost/performance barrier when upgrading to 40G or 100G.

With the increasing number of telecom carriers migrating to 40G/100G solutions, the need to continually upgrade network performance is growing. But monitoring and analyzing 2x40G/2x100G of communication brings certain challenges. The common approach requires a comprehensive system of numerous 10G lines connected to a range of appliances – but this escalates both complexity and cost.

The Link™ NT200A02 SmartNIC from Napatech enables direct analysis of 40G or 100G with just a single server. It merges upstream and downstream data so specific information can be delivered directly to the right CPU core even for fragmented traffic and GTP tunnels. This lowers the processing load on the CPUs and enables the application to efficiently analyze the target data in 1U form factor servers.

With the Link™ NT200A02 SmartNIC, applications will be able to monitor performance and analyze quality of experience even at 40G or 100G. This enables telecom operators to improve quality, while better managing the bandwidth challenges posed by rich media applications.

Cloud and data center

Enable full flow analysis of your 40G or 100G infrastructure in real-time – and keep rackspace at a minimum.

Maintaining performance while enhancing services to accommodate 40G or 100G and beyond is fundamental to the long-term viability of cloud and data center businesses. Data center managers are further challenged to retain the lowest possible CAPEX and OPEX.

With the Link™ NT200A02 SmartNIC, Napatech is helping the industry to tackle these challenges. Because of its compact design, this solution enables 2x40G/2x100G applications in 1U server platforms, thus saving rack space and cutting costs while maintaining integrity and performance.

With its intuitive plug and play features, this solution can be seamlessly integrated and significantly accelerate time-to-market, even for advanced Deep Packet Inspection (DPI) and netflow based applications. As Napatech FPGA SmartNICs provide the freedom to mix and match ports and speeds, customers can continually scale their solutions to accommodate the ever-changing market dynamics. 

Network management

Provide reliable results and insights for 40G or 100G links without compromise, in real time and with nanosecond precision.

With the colossal growth of web-based applications and cloud services, users are demanding greater access to data at faster speeds. Network operators are in continuous pursuit of more effective monitoring and analysis solutions to help them boost performance. But even the best solutions cannot deliver without completely reliable data.

The Link™ NT200A02 SmartNIC guarantees quick and accurate data delivery even at 40G or 100G. Traffic on the two 40G or 100G ports is timestamped with nanosecond precision and delivered to the network application in the right order – a huge benefit for the analysis of network traffic. This enables network solutions to instantly and effectively identify and remediate any performance issues – and ultimately helps to optimize infrastructure, increase network uptime and reduce the number of man-hours required to identify any issues. 

Ultimate tech specs

TECH SPECSLink™ NT200A02-SCC & Link™ NT200A02-NEBS
Network Interfaces• IEEE standard: IEEE 802.3 40 Gbps Ethernet support
• Network interface: 2 × QSFP+ ports
Supported Optical Transceivers• Supported QSFP+ modules: 40GBASE-SR4, 40GBASE-LR4, 40GBASE-SR-BiDi and 40GBASE-CR4
• Supported QSFP28 modules: 100GBASE-SR4 and 100GBASE-LR4
Performance• Data rate: 8 x 10 Gbps / 2 × 40 Gbps / 2 x 100 Gbps
• Typical CPU load: < 5%
Hardware Time Stamp• Resolution: 1 ns
• Stratum 3 compliant TCXO
Time Formats• PCAP-ns/-μs
• UNIX 10 ns, 1 ns
Time Synchronization• SMA interface for PPS
• RJ45 100/1000BASE-T interface for IEEE1588 PTP support
Host Interface and Memory• Bus type: 16-lane 8 GT/s PCIe Gen3
• 12 GB onboard DDR4 RAM
• Flash: Support for two boot images
• Built-in thermal protection
Statistics• RMON1 counters plus jumbo frame counters per port
• Frame and byte counters per color (filter) and per host buffer
• Counter sets always delivered as a consistent time-stamped snapshot
Environment for NT200A02-SCC-2×100/40• Operating temperature: 0 °C to 45 °C (32 °F to 113 °F)
• Operating humidity: 20% to 80%
Environment for NT200A02-NEBS-2×100/40• Operating temperature: –5 °C to 55 °C (23 °F to 131 °F) measured around the SmartNIC
• Operating humidity: 5% to 85%
Sensors• Temperature
• Power
OS Support• Linux
• Windows
Software• Napatech API for high performance and advanced features
• libpcap
• SDK tools included in source code for debugging and prototyping and as application examples
Physical Dimensions• ½-length and full-height PCIe
• Full-height PCIe
Regulatory Approvals and Compliances• PCI-SIG®
• NEBS level 3
• CE
• CB
• RoHS
• cURus (UL)

Resources and downloads

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– our engineers will help you all the way.

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