Financial Services

Algorithmic Trading is Changing the Rules of the Game
In today’s world of algorithm-driven, machine-to-machine trading, millions of shares can be traded in a nanosecond and any delay can cost millions. Financial trading is becoming ever more dependent on the health and performance of the networks it utilizes. The inability to detect and control latency can be devastating for both investor confidence in markets and trading performance.
 
We Deliver Data for Latency Analysis to Ensure Trading Runs Smoothly
Financial information providers depend on the transport of critical market data with the lowest delay possible, without compromising delivery. In order to ensure that trading runs smoothly, exchanges, trading institutions, and service providers all need reliable data delivery to the analysis application. Our solutions deliver data faster, more efficiently, and on-demand to independent network monitoring systems that are able to visualize all transactions in real time.

 

 


FINANCIAL LATENCY MEASUREMENT

Our solutions deliver data to applications that make delays visible by capturing all transactions and measuring the exact time of each trading event up to the nanosecond. This enables financial institutions to guarantee optimal performance and transparency of their trading infrastructure.

FRAUD DETECTION AND COMPLIANCE MANAGEMENT

Our solutions deliver data to applications that ensure compliance with regulations, protect trading information, and reduce the risk of confidential information leaks. This enables stock exchanges to provide a seamless, secure trading experience for their customers.

FULL LINE-RATE PACKET CAPTURE
 
Napatech accelerators are highly optimized to capture network traffic at full line-rate, with almost no CPU load on the host server, for all frame sizes. Zero-loss packet capture is critical for applications that need to analyze all the network traffic. If anything needs to be discarded, it is a matter of choice by the application, not a limitation of the accelerator.
 
Standard network interface cards (NICs) are not designed for analysis applications where all traffic on a connection or link needs to be analyzed. NICs are designed for communication where data that is not addressed to the sender or receiver is simply discarded. This means that NICs are not designed to have the capacity to handle the amount of data that is regularly transmitted in bursts on Ethernet connections. In these burst situations, all of the bandwidth of a connection is used, requiring the capacity to analyze all Ethernet frames. Napatech accelerators are designed specifically for this task and provide the maximum theoretical packet capture capacity.
OPTIMIZED PACKET BUFFERS
 
Napatech accelerators use a buffering strategy that allocates a number of large memory buffers where as many packets as possible are placed back-to-back in each buffer.  Using this implementation, only the first access to a packet in the buffer is affected by the access time to external memory. Thanks to cache pre-fetch, the subsequent packets are already in the level 1 cache before the CPU needs them. As hundreds or even thousands of packets can be placed in a buffer, a very high CPU cache performance can be achieved leading to application acceleration.
 
Buffer configuration can have a dramatic effect on the performance of analysis applications. Different applications have different requirements when it comes to latency or processing. It is therefore extremely important that the number and size of buffers can be optimized for the given application. Napatech accelerators make this possible. 
 
The flexible server buffer structure supported by Napatech accelerators can be optimized for different application requirements. For example, applications needing short latency can have frames delivered in small chunks, optionally with a fixed maximum latency. Applications without latency requirements can have data delivered in large chunks, providing more effective server CPU processing of the data. Applications that have intensive, time-consuming processing requirements can configure larger server buffers (up to 128 GB).
 
Up to 128 buffers can be configured and combined with Napatech multi-CPU distribution (see “Multi-CPU distribution”).
 
ON-BOARD PACKET BUFFERING
 
Napatech accelerators provide on-board memory for buffering of Ethernet frames. Buffering assures guaranteed delivery of data, even when there is congestion. There are three potential sources of congestion: the PCI interface, the server platform, and the analysis application.
 
PCI interfaces provide a fixed bandwidth for transfer of data from the accelerator to the application. For some accelerators, this can limit the amount of data that can be transferred from the network to the application. For example, an 8-lane PCIe Gen3 interface can transfer up to 50 Gbps of data to the application. If the network speed is 100 Gbps, a burst of data cannot be transferred over the PCIe Gen3 interface in real time, since the data rate is twice the maximum transferable rate that can be transferred over the PCIe Gen3 interface. In this case, the onboard packet buffering on the Napatech accelerator can absorb the burst and ensure that none of the data is lost, allowing the frames to be transferred once the burst has passed.
 
Servers and applications can be configured in such a way that congestion can occur in the server infrastructure or in the application itself. The CPU cores can be busy processing or retrieving data from remote caches and memory locations, which means that new Ethernet frames cannot be transferred from the accelerator.
 
In addition, the application can be configured with only one or a few processing threads, which can result in the application being overloaded, meaning that new Ethernet frames cannot be transferred. With onboard packet buffering, the Ethernet frames can be delayed until the server or the application is ready to accept them. This ensures that no Ethernet frames are lost and that all the data is made available for analysis when needed.
MULTI-PORT PACKET MERGE
 
Napatech accelerators typically provide multiple ports. Ports are usually paired, with one port receiving upstream packets and another port receiving downstream packets. Since these two flows going in different directions need to be analyzed as one, packets from both ports must be merged into a single analysis stream. Napatech accelerators can merge packets received on multiple ports in hardware using the precise time stamps of each Ethernet frame. This is highly efficient and offloads a significant and costly task from the analysis application.
 
There is a growing need for analysis appliances that are able to monitor and analyze multiple points in the network, and even provide a network-wide view of what is happening. Not only does this require multiple accelerators to be installed in a single appliance, but it also requires that the analysis data from all ports on every accelerator be correlated.
 
With the Napatech Software Suite, it is possible to merge the analysis data from multiple accelerators into a single analysis stream. The merging is based on the nanosecond precision time stamps of each Ethernet frame, allowing a time-ordered merge of individual data streams.
 
HARDWARE TIME STAMP
 
The ability to establish the precise time when frames have been captured is critical to many applications. 
 
To achieve this, all Napatech accelerators are capable of providing a high-precision time stamp, sampled with 4 nanosecond resolution, for every frame captured and transmitted.
 
At 10 Gbps, an Ethernet frame can be received and transmitted every 67 nanoseconds. At 100 Gbps, this time is reduced to 6.7 nanoseconds. This makes nanosecond-precision time-stamping essential for uniquely identifying when a frame is received. This incredible precision also enables you to merge frames from multiple ports on multiple accelerators into a single, time-ordered analysis stream.
 
In order to work smoothly in the different operating systems supported, Napatech accelerators support a range of industry standard time stamp formats, and also offer a choice of resolution to suit different types of applications.
 
64-bit time stamp formats:
  • 2 Windows formats with 10-ns or 100-ns resolution
  • Native UNIX format with 10-ns resolution
  • 2 PCAP formats with 1-ns or 1000-ns resolution
TIME SYNCHRONIZATION
 
With hardware time stamps, individual frames can be time-stamped with high precision. However, to assure that the time stamps in frames from different accelerators in the same, or even different, appliances are comparable, the clocks driving the time stamp engines must be synchronized. Napatech has advanced HW time synchronization between accelerators.
 
There are various mechanisms to provide time synchronization, including synchronization with the operating system clock, known as OS time synchronization. However, for the best accuracy, a hardware-based time synchronization solution based on an industry standard time synchronization protocol should be used. For many applications that rely on accurate time stamps to understand when an event occurred or accurately measure delay across high-speed networks, nanosecond accuracy is essential.
 
Napatech accelerators provide flexible support for a range of standard time synchronization mechanisms. Dedicated time synchronization connectors enable direct time signal input from an external time source and retransmission of time synchronization signals to other accelerators. In this way, multiple accelerators in the same host or in different hosts will operate in lockstep in a large synchronous installation.
 
Napatech accelerators are designed to accommodate the time synchronization mechanisms available during deployment. With dedicated ports that can accommodate multiple time synchronization protocols, Napatech provides a flexible solution that does not need to sacrifice ports which are normally used for capture and transmission.
 
The following list contains some of the time synchronization mechanisms supported:
 
  • IEEE 1588-2008 /PTPv2 Time Synchronization
  • PPS Time Synchronization
  • GPS and CDMA Time Synchronization over PPS and Server Serial Port
  • OS Time Synchronization
200G PERFORMANCE SOLUTION
 
Napatech 200G Performance Solution is based on two PCI-SIG® certified NT100E3- 1-PTP accelerators, each providing a single 100G port with full throughput and zero packet loss under all conditions. Upstream and downstream are combined using Intelligent Hardware Interconnect. This allows specific flows to be combined and directed to the right CPU cores for processing.
 
Learn more about the 200G Performance Solution.
200G COMPACT SOLUTION
 
Use cutting-edge network acceleration technology to add real-time line rate performance to your application. The Compact 200G Accelerator NT200A01 provides full packet capture and analysis of network data at 200G with zero packet loss.
 
Learn more about the 200G Compact Solution.
NT100E3-1-PTP
 
The PCI-SIG® certified NT100E3-1-PTP accelerator can be used for packet capture and analysis of Ethernet LAN data at 100 Gbps with zero packet loss for all frame sizes. Intelligent features accelerate application performance with extremely low CPU load. Flexible time synchronization support is included with a dedicated PTP port. 
 
The accelerator also comes in a NEBS level 3 compliant variant.
 
Learn more about NT100E3-1-PTP.
NT80E3-2-PTP
 
The PCI-SIG® certified NT80E3-2-PTP accelerator provides full packet capture and analysis of Ethernet LAN at 80 Gbps with zero packet loss for all frame sizes. Intelligent features accelerate application performance with extremely low CPU load. Flexible time synchronization support is included with a dedicated PTP port.
 
The accelerator also comes in a NEBS level 3 compliant variant.
 
Learn more about NT80E3-2-PTP.
NT40E3-4-PTP
 
The PCI-SIG® certified NT40E3-4-PTP accelerator provides full packet capture and analysis of Ethernet LAN at 40 Gbps with zero packet loss for all frame sizes. Intelligent features accelerate application performance with extremely low CPU load. Flexible time synchronization support is included with a dedicated PTP port. 
 
The accelerator also comes in a NEBS level 3 compliant variant.
 
Learn more about NT40E3-4-PTP.
NT20E3-2-PTP
 
The NT20E3-2-PTP accelerator provides full packet capture and analysis of Ethernet LAN at 20 Gbps with zero packet loss for all frame sizes. Intelligent features accelerate application performance with extremely low CPU load. Flexible time synchronization support is included with a dedicated PTP port.
 
The accelerator also comes in a NEBS level 3 compliant variant.
 
Learn more about NT20E3-2-PTP.
NT4E2-4-PTP
 
The NT4E2-4-PTP accelerator provides full packet capture and analysis of Ethernet LAN at 4 Gbps with zero packet loss for all frame sizes. Intelligent features accelerate application performance with extremely low CPU load. Flexible time synchronization is included with a dedicated PTP port.
 
Learn more about NT4E2-4-PTP.
NT4E-4-STD
 
The NT4E-STD is a 4-port 1 Gbps accelerator that provides full line-rate data capture and nanosecond precision time-stamping capabilities that can accelerate network applications and off-load the server CPU. The 4 ports on NT4E-STD accelerators enable full-duplex monitoring of a network link (Rx and Tx traffic). 
 
Learn more about NT4E-4-STD.
PANDION
 
Pandion Flex is your cost-efficient platform of choice for ultrafast, highly reliable real-time capture, indexing and search of data across Napatech’s network recorder. Pandion is available in multiple rate interface options and configurable storage to over 600TB.
 
Learn more about Pandion.
NAC
 
Use cutting-edge network acceleration technology to add real-time line rate performance to your PCAP solution – with no software integration required. Napatech network acceleration cards (NACs) provide full packet capture and analysis of network data with zero packet loss.
 
Learn more about our NACs.