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F2070X Infrastructure Processing Unit (IPU)

2×10/25G, 8×10/25G, 2x100G

Powerful Intel®-based Infrastructure Processing Unit (IPU)
The Napatech F2070X Infrastructure Processing Unit (IPU) is a 2x100Gbe PCIe card with an Intel Agilex® AGFC023 FPGA and an Intel® Xeon® D SoC. The unique combination of FPGA and full-fledged Xeon CPU on a PCI card allows for unique offload capabilities. Coupled with Napatech software, the F2070X is the perfect solution for network, storage and security offload and acceleration. It enables virtualized cloud, cloud-native or bare-metal server virtualization with tenant isolation.

Customization on demand
The F2070X uniquely offers both programmable hardware and software, to tailor the IPU to the most demanding and specific needs in your network, and to modify and enhance its capabilities over the life of the deployment. It is based on the Intel Application Stack Acceleration Framework (ASAF) that supports the integration of software and IP from Intel, Napatech, 3rd parties and homegrown solutions. This one of a kind architecture enables hardware performance and the speed of software innovation.

Scalable platform
The Napatech F2070X comes in a standard configuration, and includes support for several combinations of Intel® FPGAs, Xeon® D processors, and memory. This enables tailored platform configurations matching requirements for specific use cases.

Napatech F2070X IPU

Compatible Software

Link Storage Software

Link-Storage™ Software

Maximizes the performance of data center storage based on NVME over TCP (NVME/TCP).

Link-Security software

Link-Security™ Software

Maximizes the performance of data center security based on Transport Layer Security (TLS) encryption.

Link-Virtualization™ Software

Link-Virtualization™ Software

Maximizes the performance of data center networking for Infrastructure-as-a-Service platforms.

Watch video by NextGenInfra where Charlie Ashton, Senior Director of Business Development from Napatech explains how
Infrastructure Processing Units (IPUs) promise big gains in efficiency for data center operations.

F2070X IPU


Napatech upholds the highest quality, environmental and safety standards, and complies with all applicable regulations across regions. This helps our customers to realize a seamless integration without delays – and ensures error-free operation throughout the product life cycle.

Ethernet Front Port Compliance

The IPU design maximizes mechanical and electrical front port margin, securing trouble-free operation with the optical or electrical modules of the customer’s choice.

The thermal design is validated dissipating the maximum power level as standardized for the given form factor. Margin on the data interface has been optimized tuning the equalization parameters of the transceivers hosting the front port channel, maximizing EYE margin to the relevant standard.

EMC Compliance

All Napatech designs have passed EMC compliance testing for major regions, including Europe and North America. By ensuring compliance as an integral part of the design, the risk of delays is eliminated. Moreover, the EMC testing has been performed in a mainstream server, potentially directly applicable to the use case.

Environmental Compliance

The end product (server + installed IPU) must adhere to regional environmental legislation. To enable trouble-free server integration, Napatech IPUs are manufactured using only materials that fully comply with the current RoHS, REACH and proprietary Tier 1 legislation.

Full compliance from early inception eliminates the risk delays and product withdrawal due to authority intervention.

Event Handling & System Monitoring

In order for the IPU to become an integral part of the server environment and maximize uptime, it needs to monitor and expose key performance metrics to the application during operation. Napatech IPUs monitor the following metrics:

  • Hot spot temperatures
  • Key supply voltages and currents
  • PCI protocol events
  • General system events

PCI Compliance

With the PCI interface on the IPU dictated by the server plane, the hardware maximizes mechanical and electrical PCI margin, ensuring trouble-free operation in the server and server slot(s) of the customer’s choice. All designs have passed relevant PCI-SIG tests and have been adopted on the PCI-SIG integrators list.

Safety Compliance

To enable trouble-free server integration, Napatech IPUs are fully compliant with all applicable safety standards.

By ensuring safety compliance as an integral part of the IPU design, the risk of delays is eliminated. Compliance testing is performed in a mainstream server, potentially directly applicable to the use case.

Conflict Minerals Compliance

To ensure quick and trouble-free server integration, Napatech IPUs are manufactured using only materials that fully comply with the relevant Conflict Mineral Legislation. For US based IPU integrators, this facilitates submission of the mandatory Conflict Mineral report to SEC.

Shock & Vibration Robustness

Many server environments expose the IPU to substantial shock and vibration, predominantly during the transportation phase. To ensure trouble-free server integration and operational robustness throughout the product life cycle, validated design aspects include:

  • Cooling enclosure for superior mechanical stiffness
  • Key exposed components are under-filled (glued) to the PCB
  • Shock robustness validated against JESD22-B110A
  • Vibration robustness validated against ASTM D4169-09

Feature Highlights and Specifications


FPGA Device and Memory
  • Intel Agilex® AGFC023
    • 2.3M LEs, 782.4K ALMs, 10.4K M20Ks
    • Hardened crypto
  • 4×4 GB DDR4 (ECC, 40b, 2666MT)
SoC Processor and Memory
  • Intel® Xeon® D-1736 processor
    • 8 Cores, 16 Threads
    • 2.3GHz, 3.4 GHz Turbo Freq.
    • 15 MB Cache
  • 2×8 GB DDR4 (ECC, 72b, 2933MT)
  • Up to 2 TB in M.2 NVMe x4 (2230/2242) slot for Operating System and applications
PCI Express Interfaces
  • PCIe Gen 4.0 x16 (16 GT/s) to the host
  • PCIe Gen 4.0 x16 (16 GT/s) between the FPGA and SoC
Front Panel Network Interfaces
  • 2-ports QSFP28/56
  • 2x100GBASE-LR4/SR4/CR4
  • 2×10/25GBASE-LR/SR/CR (QSFP/SFP adapter)
  • 8×10/25GBASE-SR/CR (breakout cable)
  • Dedicated RJ45 management port
Supported Compute and Memory Devices (Mount Options)
  • FPGA: Intel Agilex® AGFC022 or AGFC027
  • CPU: All Intel® Xeon® D-1700 Series processors
  • FPGA Memory
    • 3×4 GB DDR4 (ECC, 40b, 3200 MT) + 1×8 GB DDR4 (ECC 72b 3200 MT)
  • CPU Memory
    • 3×8 GB DDR4 (ECC, 72b, 2900MT)
    • 3×16 GB DDR4 (ECC, 72b, 2900MT)
  • Full-height, half-length, dual-slot PCI form factor Power and Cooling
Power and Cooling
  • Max power consumption for standard HW configuration: 150W
  • Max power dissipation supported by platform: 250W
  • NEBS compliant passive cooling
Time Synchronization (Mount Options)
  • Dedicated PTP RJ45 Port
  • External SMA-F Connector (PPS/10MHz I/O)
  • Internal MCX-F Connector (PPS/10MHz I/O)
  • Stratum 3 TCXO or Stratum 3e OCXO
  • IEEE1588v2 Suppor
Board Management
  • Ethernet, USB (Front panel), UART (Internal) connectivity
  • Secure FPGA image update
  • Wake-on-LAN
  • MCTP over SMBus
  • MCTP over PCIe VDM
  • Dedicated NC-SI RBT internal port
  • PLDM for Monitor and Control (DSP0248)
  • PLDM for FRU (DSP0257)
CPU Operating System
  • Fedora 37 (Linux Kernel T.BD)
  • PXE Boot support
  • Full shell access via SSH and UART
Environment and Approvals
  • EU, US, APCJ Regulatory approvals
  • Thermal, Shock, Vibration tested
  • UL Marked, RoHS, REACH compliant
  • Temperature range: -5 to +45 deg. C.
  • ASHRAE class A2
Application Stack Acceleration Framework (ASAF)
  • Framework for embedding customer Accelerator Functional Units (AFU) implementing workload acceleration/offload in FPGA
  • 6 AFUs supported
  • Throughput up to 200Gbps
  • Look-aside and inline AFU configurations
  • Pre-integrated AFUs for Host virtio-net DMA, SoC virtio-net DMA and packet processor w. fundamental NIC functions
Network Offload
  • Supports packet processor with basic NIC functionality
  • Supports packet processor implementing Open vSwitch hardware offload of the dataplane
  • OvS hardware offload at the Megaflows layer (wildcard matches)
  • 1024 MegaFlows cache supporting millions of exact flows
  • Supports VLAN, QinQ, and VxLAN encapsulation/decapsulation in hardware
  • OvS Control plane on the host or on the SoC
  • Exposes VirtIO-net virtual interfaces as PFs or VFs (SR-IOV)
Storage Offload
  • NVMeOF TCP offload
  • Presents 16 Block devices to the Host (Virtio-Blk)
  • Compatible with the VirtIO-Block drivers present in the latest RHEL and Ubuntu Linux distributions
  • No proprietary software and drivers required in the Host
  • No network interfaces exposed to the Host
  • NVMe/TCP initiator running on the SoC
  • Offloads all NVMe/TCP operations from the host CPU to the IPU
  • No access to the SoC from the Host (Airgap)
  • Storage configuration over SPDK RPC interface
  • NVMe/TCP Multipath support
  • 2x100G connectivity to the storage network
Security Offload
  • TCP+TLS offload
  • Present up to 16 network devices to the Host (Virtio-net)
  • 2x100G Ethernet front-port connectivity
  • TLS 1.2/1.3 encryption offload
  • Openssl support
  • Nginx based HTTP(s) reverse proxy with caching
  • WebSockets support
  • Load balancing to host
  • Web server acceleration (reduced page load time) with static file caching and image optimization
Supported Hardware and Transceivers
  • F2070X IPU:
    • 100GBASE-LR4/SR4/CR4
    • 10/25GBASE-LR/SR/CR

Resources and downloads

Data Sheet

Solution Description

Solution Description

Solution Description

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Find out if the Napatech F2070X IPU is right for you
– our engineers will help you all the way.