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FPGA SMARTNICS

Link Inline Software
for Napatech FPGA-based SmartNICs

Napatech SmartNICs and Link™ Inline Software provide a hardware-based solution for accelerating network and security applications dramatically increasing application performance while reducing CPU consumption. The Link™ Inline Software provides a processing architecture which offloads and accelerates flow aware application dataplanes offering the ability to scale open source and custom applications to >100 Gbps in standard servers with lower complexity and enhanced scalability than alternatives.

Link™ Inline Software supports a broad range of applications and use cases – and can immediately improve an organization’s ability to scale critical networking use cases.

Key Benefits

Napatech provides the unique combination of the industries highest performance FPGA-based SmartNIC with software for offload and accelerate Inline networking and security applications.

High Performance

Scale network and security applications to 100Gbps

Extremely Low Latency

Minimize network delays for inline applications

Significantly Reduced CPU Utilization

Return CPU cores to applications and services

Total Cost of Ownership

Cost effective scaling for your data center

Reconfigurability

Completely programmable for custom requirements

Environmentally Sound

Lower power, space, and cooling

Solution Overview

Networking and cybersecurity applications and services are often deployed as software in high volume, low-cost standard servers. Many, however, require higher throughput and lower latency than can be provided by compute platforms with basic network interface cards (NICs).

Napatech’s Link™ Inline software and SmartNIC hardware provides the ability to scale open source and custom networking and security applications to >100 Gbps in standard servers. This stateful, flow-aware solution allows applications running in software to dynamically and programatically update processing actions in SmartNIC hardware on a per flow basis, tightly coupled with the application via simple to use rules or standards-based APIs. The solution scales to greater than 100 million flows, each monitored in a stateful manner with over 2 million flow setups and teardowns per second with extremely low latency.

Slide Cut-through Flows Dropped / blocked flows Flows relevant for application inspection

Key Features

Napatech Link™ Inline Software provides the Napatech SmartNIC family with a robust feature set and extendable architecture allowing configurable, flow-based offload and acceleration for networking and security applications.

Link Inline Software for Napatech

Stateful Flow Processing

200 Gbps Throughput

2 Million Flow setups / second

100 million flow table entries

Inline, Packet Capture, or Tap modes

Configurable packet classification / match fields

Extensive actions

Load balancing to application instances

Link™ Inline Block Diagram

Compatible Napatech FPGA-based SmartNICs

The Link™ Inline Software is available for our family of FPGA-based SmartNICs.

NT200A02 SmartNIC

8x10G, 2×10/25G, 4×10/25G, 2x40G, 2x100G

The NT200A02 SmartNIC is a full height, half length QSFP28 PCIe card based on a powerful FPGA-based architecture which enables 8x10G, 2×10/25G, 4×10/25G, 2x40G or 2x100G applications.

NT100A01 SmartNIC

4×1/10G, 4×10/25G

The NT100A01 SmartNIC is a full height, half length SFP28 PCIe card based on a powerful FPGA-based architecture, which enables 4×1/10G or 4×10/25G applications.

These SmartNICs offer flexibility to create high-performance solutions in server platforms for supporting network infrastructures up to 100G and can be reconfigured to support specific SmartNIC functionality. They are available in both a self-contained cooling and passive cooling version.

Tech specs

FEATURES Link Inline Software for Napatech FPGA SmartNICs
Rx Packet Processing • Line rate Rx up to 100 Gbps for packet size 64 – 10,000 bytes
• Multi-port packet merge, sequenced in time stamp order
L2, L3 and L4 protocol classification • L2: Ether II, IEEE 802.3 LLC, IEEE 802.3/802.2 SNAP
• L2: PPPoE Discovery, PPPoE Session, Raw Novell
• L2: ISL, 3x VLAN, 7x MPLS
• L3: IPv4, IPv6
• L4: TCP, UDP, ICMP, SCTP
• L2 and L3/L4 (IP/TCP/UDP) Tx checksum generation
• L2 and L3/L4 (IP/TCP/UDP) Rx checksum verification
Tunneling support • GTP, IP-in-IP, GRE, NVGRE, VxLAN, Pseudowire, Fabric Path
General purpose filters • Pattern match, network port, protocol, length check, error conditions
Stateful flow management (NT100A01 and NT200A02) • Configurable flow definitions based on 2-, 3-, 4-, 5- or 6-tuple
• Up to 160 million bidirectional IPv4 or IPv6 flows (NT200A02)
• Up to 100 million bidirectional IPv4 or IPv6 flows (NT100A01)
• Learning rate: 3 million flows/sec
• Flow match/actions: forward to specific host Rx queue, drop, fast forward to network port, update metrics in flow record
• Flow termination: TCP protocol, timeout, application-requested
• Flow records: Rx packet/byte counters and TCP flags, delivered to application at flow termination
Hash keys • Custom 2 × 128 bits and 2 × 32 bits with separate bit masks
• Symmetric hash keys
• Protocol field from inner or outer headers
Load distribution • Hash key, filter-based or per flow
• To local CPU cores via host buffers/queues
Packet descriptors and metadata • PCAP and Napatech descriptor formats
• Time stamp, network port ID, header offsets
• Hash key, color/tag
• 64-bit pointer for flow lookup
• 64-bit correlation key with maskable fields (packet fingerprint)
• Protocol and error information
Slicing • Dynamic offset or fixed offset from start or end of packet
Tx Packet Processing • Line rate Tx up to 100 Gbps for packet size 64 – 10,000 bytes
• Per-port traffic shaping
• Port-to-any-port forwarding
Latency • Port to port: < 5 us
• Port to host: < 30 us
Host Buffers and Queues • Rx queues: 128, Tx queues: 128
• Rx buffer size: 16 MB – 1 TB, Tx buffer size: 4 MB
Advanced Statistics • Extended RMON1 per port
• Packets and bytes per filter/color and per stream/queue
Time Stamping and Synchronization • OS time, PPS and IEEE 1588-2008 PTP V2
• NT-TS synchronization between Napatech SmartNICs
• Time stamp formats: Unix 10 ns, Unix 1 ns, PCAP 1 us, PCAP 1 ns
• Rx time stamp with 1 ns resolution
Monitoring Sensors • PCB temperature level with alarm
• FPGA temperature level with alarm and automatic shutdown
• Temperature of critical components
• Individual optical port temperature or light level with alarm
• Voltage or current overrange with alarm
• Cooling fan speed with alarm
Supported OS • Linux kernel 3.0 – 3.19, 4.0 – 4.18, 5.0 – 5.11 (64-bit)
Supported APIs • libpcap v. 1.7.3, 1.8.1, 1.9.0
• DPDK v. 20.11
• NTAPI (Napatech API)
Supported Hardware and Transceivers

NT200A02:
• 1000BASE-T, SX, LX, ZX
• 10GBASE-SR, CR, LR, ER and breakout to 4x10GBASE-SR, CR, LR
• 25GBASE-SR, LR, LR-BiDi and breakout to 4x25GBASE-SR, LR
• 40GBASE-SR4, SR-BiDi, CR4, LR4
• 100GBASE-SR4, SR-BiDi, LR4

 

NT100A01:
• 1000BASE-T, SX, LX, ZX
• 10GBASE-SR, CR, LR, ER
• 25GBASE-SR, LR, LR-BiDi

Resources and downloads

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