Future-proof FPGA Platforms: The Longevity and Upgradability

Following on from my last blog – “History of Ethernet – New “Rules” and The Ongoing Evolution”, in this blog, I will be discussing the evolution of FPGA technology supporting FPGA based network acceleration cards (NACs). This evolution has enabled the current options to design very flexible HW platforms, supporting a broad range of existing and new use cases, all with an extended lifetime/horizon.

With the ambitious headline, I think a good start would be to establish what to expect from a future-proof FPGA based NAC.

Any future-proof FPGA-based NAC HW platform should support:

• Ethernet link speeds and types available currently and in the near future, through attractive front port connectivity, see Figure 1.
• Different FPGA size configuration, providing the customer with the right cost/feature ratio options, enabling competitive product offerings

Figure 1: Current and future Ethernet link speeds and types

Historically, FPGA-based NACs have deployed the so-called PHY devices in the data path between the FPGA and the Ethernet front port. The discreet silicon PHY device handles the physical layers of the Ethernet protocol stack.

For the highest port rates, the PHY device has typically been a necessity as it added functionality not available in current FPGA technology. For other port rates the PHY device represents an attractive compromise between cost and NAC features.

Key drivers for the deployment of the PHY devices:

1. FPGA transceiver speed limitations
2. Logical resource constraints in the FPGA
3. Minimizing BOM cost

Whereas the PHY device neatly compensates for above FPGA limitations, it typically restricts the design in the number of supported Ethernet link speeds and potential types.

25G transceiver technology was introduced in the 28nm FPGA process node, but was only made available in a few high-end device options, available at a substantial cost, compared to the mainstream device options. For good reasons, besides the cost factor, the initial 100G FPGA-based NAC offerings deployed PHY devices implementing the required so called gearbox functionality and optional error correction functionality. As with the previous PHY application, the gearbox PHY restricts these designs in the number of supported Ethernet link speeds to just 100G.

With the introduction of the latest 20nm FPGA families from Xilinx and Intel (former Altera), the FPGA technology is on par with the current and near term future Ethernet link speeds obsoleting the need for the PHY companion devices.

Figure 2: Current 20nm FPGA options

The newly released Napatech NT200A01 implements a PHY-less FPGA-based NAC design. The product has been designed for the currently available Xilinx Virtex Ultrascale 20nm FPGA technology and the next generation Xilinx Virtex Ultrascale+ 16nm FPGA technology. This industry pioneering option to operate two FPGA process nodes on the same HW platform has been enabled through footprint compatibility from the FPGA vendor. The HW platform is currently supported by a 2 port 100G feature set and support will shortly be followed by the release of a 2 port 40G feature set.

Potential future feature set release candidates include:

1. Up to 8 port 1G
2. Up to 8 port 10G
3. Up to 8 port 25G
4. Up to 4 port 50G, 2 lane “consortium” variant

From a multi-link speed customer perspective, a PHY-less FPGA based NAC design poses the following number of obvious benefits:

1. Ability to source many different product variants with the same NAC part number
   1. Reducing the amount of required HW qualification resources
   2. Collecting volume on one/few NAC part numbers pleasing logistics and pricing
2. Ability to introduce multi-link speed product variants eventually handling all major link speeds and types, on the same ports, through dynamic reconfiguration.
3. Restriction of the required knowledge base to one platform.

In my next blog entry, I will be discussing the related front port connectivity options maximizing the market value of the future-proof FPGA platform discussed in this blog. I will touch on the following points:

1. Physical form factor
2. Supported link types
3. Supported link speeds

So stay tuned!