Peter Sanders, VP Field Applications Engineering at Napatech, looks at the importance of zero packet loss to a successful IDS deployment - measured by its effects on intrusion alert generation and file extraction.
In this blog, Chief Product Architect Alex Agerholm looks at the standard definition of network flows and explores the great potential that can be realized for lookup technology by seeing beyond conventional flow compositions.
For efficiency, a lot of monitoring and analysis tools focus on flow records to detect anomalies in the network - and only dive to the underlying packet level if needed. In this blog, Chief Product Architect Alex Agerholm discusses typical use cases, looks at NetFlow/IPFIX acceleration and speculates on the imminent future of flow processing.
Following some recent work to run VXLAN using HW offload, the Napatech OVS offload initiative now explores another important feature: mirror offload. Learn how this enables monitoring without affecting performance of the overall system.
The new Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA can now run Napatech firmware. Chief Technology Architect Michael Lilja explores Intel's OPAE framework and takes a closer look at the PAC hardware and Napatech value-add.
Peter Sanders, VP Field Applications Engineering at Napatech, talks about the importance and benefits of continuous packet capture for network security.
A blog article by Alex Agerholm, who explains and delves into the concept of packet capture as a service in a virtualized environment.
In his latest blog, Sven talks about the network traffic replay at 100G and its benefits in a test scenario.
Packets burst into contiguous memory provide a huge performance benefit due to L1 HW prefetching and optimal PCIe utilization.
Following on from my last blog - “History of Ethernet - New "Rules" and The Ongoing Evolution”, in this blog, I will be discussing the evolution of FPGA technology supporting FPGA based network acceleration cards (NACs).