Charlie Ashton, Senior Director Business Development at Napatech, looks at the importance of power and cost in edge data centers – the process of offloading virtual switching from server CPUs onto programmable Smart Network Interface Cards (SmartNICs).
In his latest article, Claus Ek delves into his expertise on hardware to throw light on some of the requirements that need addressing to make a successful high-volume use case for FPGA-based reconfigurable computing platforms.
The final in the 3-part series of articles by Dan Joe, where he explores the various stages of reconfigurable computing.
The second in the 3-part series of articles by Dan Joe, where he explores the various stages of reconfigurable computing.
The first in the 3-part series of articles by Dan Joe, where he explores the various stages of reconfigurable computing.
In his latest blog, Sven talks about the network traffic replay at 100G and its benefits in a test scenario.
FPGA has shown that it can provide significant acceleration and a high level of reconfigurability and doing all that with an efficient compute power per watt.
So where does all this lead and who is the winner?
In the run-up to SDN World Congress in The Hague, it is interesting to note that it was at this very show in Dusseldorf 5 years ago that the original NFV whitepaper was first presented. How time flies!
I am writing this blog article in continuation of my previous blog – “Future-proof FPGA platforms the longevity and upgradability”. In this blog entry, I discuss the available pluggable front port technology, complementing the flexible properties of the described future-proof FPGA-based SmartNICs.
Following on from my last blog - “History of Ethernet - New "Rules" and The Ongoing Evolution”, in this blog, I will be discussing the evolution of FPGA technology supporting FPGA based network acceleration cards (NACs).