Following some recent work to run VXLAN using HW offload, the Napatech OVS offload initiative now explores another important feature: mirror offload. Learn how this enables monitoring without affecting performance of the overall system.
Lately, Napatech has been working on a full OVS offload implementation. See how we've achieved a 6x performance gain compared to a basic OVS+DPDK solution running on a standard NIC.
The new Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA can now run Napatech firmware. Chief Technology Architect Michael Lilja explores Intel's OPAE framework and takes a closer look at the PAC hardware and Napatech value-add.
Today virtual switches like OVS and VPP implement ACL in SW. ACL is a run-through-all-until-match rule matcher and is therefore more expensive than a simple hash based lookup mechanism. ACL HW acceleration can make a huge difference for performance.
VPP - Vector Packet Processing is a open-source project with high community activity. How does it perform running on Napatech NICs?
TRex is used to show that 64 byte packet generation at 100Gbps on a 100GbE link is achievable using a standard server and a Napatech NIC.
Packets burst into contiguous memory provide a huge performance benefit due to L1 HW prefetching and optimal PCIe utilization.
Acceleration via NICs in DPDK has so far been via proprietary APIs and only on limited number of NICs. DPDK 17.02 rte_flow will change that.
The 16.07 release of DPDK introduces a new packet capture framework, which will allow users to capture traffic from existing devices/ports/queues and dump the packets to a pcap file...
I was recently at the Red Hat Summit in San Francisco. This is the event that today has become synonym with open source solutions, one of the biggest trends to have driven the technology...