When it comes to balancing long-term development and short-term customer needs it is all about finding the right process. In his first blog article, Ulrik Moller looks into the benefits of combining stage gate and agile process models for product development.
The second in the 3-part series of articles by Dan Joe, where he explores the various stages of reconfigurable computing.
The first in the 3-part series of articles by Dan Joe, where he explores the various stages of reconfigurable computing.
A blog article by Alex Agerholm, who explains and delves into the concept of packet capture as a service in a virtualized environment.
VPP - Vector Packet Processing is a open-source project with high community activity. How does it perform running on Napatech NICs?
As a continuation to his previous blog - “Flexible Pluggable Front Port Technology”, in the current blog Claus Ek focuses on the latest addition to the QSFPx form factor family - the QSFP-DD.
In his latest blog, Sven talks about the network traffic replay at 100G and its benefits in a test scenario.
FPGA has shown that it can provide significant acceleration and a high level of reconfigurability and doing all that with an efficient compute power per watt.
So where does all this lead and who is the winner?
In the run-up to SDN World Congress in The Hague, it is interesting to note that it was at this very show in Dusseldorf 5 years ago that the original NFV whitepaper was first presented. How time flies!
TRex is used to show that 64 byte packet generation at 100Gbps on a 100GbE link is achievable using a standard server and a Napatech NIC.